1. Field of the Invention
The present invention relates to a power amplifying apparatus having a dual-current control mode, which operates in one of two different current control modes according to a control current magnitude.
2. Description of the Related Art
In general, a power amplifier module (PAM) adjusts output power by adjusting the amount of current flowing in a main stage. Namely, the current flowing through the main stage flows through a power p-type metal-oxide-semiconductor field-effect transistor (PMOS FET) of a main low dropout (LDO) regulator, and here, the amount of current flowing into a drain and a source of the PMOS FET may be adjusted by adjusting a current sensor.
In the related art, a bias control circuit of the PAM using the main LDO regulator includes a current mirror circuit and an operational amplifier in order to control a bias.
Here, the current mirror circuit may include a transistor mirror circuit adjusting a bias current by using a transistor and a resistor mirror circuit adjusting a bias current by using a resistance ratio.
First, the existing transistor mirror circuit has a current control scheme using a metal-oxide-semiconductor field-effect transistor (MOS FET). Namely, this scheme uses a concept in which, in two MOS FETs, i.e., first and second MOS FETs, forming a current mirror circuit, when a gate voltage Vg, a source voltage Vs, and a drain voltage Vd are equal, the ratio between currents flowing in the respective first and second MOS FETs is constant.
Namely, a feedback loop is formed such that bias voltages of the two first and second MOS FETs are equal, the gate voltage Vg and the source voltage Vs are commonly applied, and drain voltages Vd1 and Vd2 of the two first and second MOS FETs are equal. Here, when a control current is adjusted, a current Ipa of an RF amplifier may be adjusted by the ratio between the sizes of the MOS FETs.
However, the following problem may be encountered in the case of a transistor mirror circuit. That is, when an RF signal is applied in a state in which the drain to source voltage Vds of the first or second MOS FET is low, the RF signal is rectified to generate a DC component, distorting the current ratio between the first and second MOS FETs.
In order to solve the problem of the related art, when the drain-to-source voltage Vds is increased to be as high as about 0.6V, a loss of power may be generated by a voltage drop.
Next, the existing resistor mirror circuit uses a concept in which a current ratio may be adjusted according to a resistance ratio when the voltages across first and second resistors are equal.
Namely, a feedback loop is formed such that voltages applied to the first and second resistors are equal, a control voltage is common, and first and second voltages V1 and V2 formed at the other ends of the first and second resistors are equal.
However, the resistor mirror circuit has a problem in which, in a case in which the voltage applied to the second resistor R2 is intended to be reduced to enhance power efficiency, if a second resistance is low, a very low voltage may be applied when current flowing in a power amplifier is low.
For example, if a voltage drop of 0.1V is generated in the second resistor R2 when a current of 1 A flows across the second resistor R2, only 1 mV voltage is applied when 10 mA flows across the second resistor R2. Thus, in consideration of the fact that S/N must be generally 60 dB or higher, when a noise level is 1 uV or higher, it may fail to satisfy an international standard.
Differently, when resistance is increased, a large voltage drop may be generated due to high resistance, degrading output and efficiency.